Chip Gallery

This is a list of all (completed) tapeouts or chip-design related projects I’ve ever done. Everything is listed in chronologically reverse order of completion, with the latest project first and the oldest last.
GitHub repos, documentation and related posts on this site are linked where applicable.


WS02 Multi-Project die

Multi-project die for second wafer.space shuttle run, containing mostly the same IP as the WS01 die, but now fully implemented using my custom SCL. Also contains layouts generated using FeatherLane, my custom RTL to Layout flow. Improved versions of the DACs are also present.

Repo

WS01 Multi-Project die

Multi-project die for first wafer.space shuttle run, containing a RV32IMA_Zicsr_Smrnmi core, various retro computing chip replicas and my first attempt at an analog layout outside of Standard Cells: a set of 12-bit DACs.

Repo Documentation

Custom Standard Cell Library (gf180)

Another SCL of 42 unique cell types, the first to use gf180’s 3.3V FET devices. Also tuned for high-performance. Officially integrated into Open PDKs.
Node: gf180mcuD
Tools used: Magic, ngspice, LibreLane

Repo

Custom Standard Cell Library

An entire SCL of 36 unique cell types, fully characterized and ready to use in the LibreLane flow, tuned for high-performance.

Node: sky130A
Tools used: Magic, ngspice, LibreLane

Repo

Minimalfab Binary Ripple Counter

Created for the Minimalfab Design Contest, this layout is a binary ripple counter with 5 stages, made to fit by using special compact implementations of the DFF and XOR functions.
Won grand prize in one of two categories.

Node: ICPS2023_5
Tools used: KLayout, ngspice, xschem

Repo & Docs

CI2406 Multi-Project

Multi-project group tapeout with multiple designs from me. Most notably a custom architecture VLIW, explicitely parallel 32-bit CPU with 3 execution units. Otherwise, contains recreations of historic CPUs in a preservation effort.

Node: sky130A
Tools used: Verilog, OpenLane, iverilog

Repo Documentation

AS2650-2 MCU

8-bit Microcontroller based on the AS2650-1 CPU architecture, with 4KiB SRAM and integrated serial ports, GPIO, timers, interupt vectoring and sound processor.

Node: gf180mcuD
Tools used: Verilog, OpenLane, iverilog, verilator

Repo Bring-up Repo Documentation Post

GFMPW-1 Multi-Project

Multi-project die for GFMPW-1 containing custom CPU/MCU architectures, audio devices and application-specific circuits. Most notable are a fully-custom RV32IM core and ultra-compact bit-serial embedded core.

Node: gf180mcuD
Tools used: Verilog, OpenLane, iverilog, verilator

Repo Bring-up Repo Documentation Post

AS2650-1 Microprocessor

Submission to GFMPW-0 containing a 8-bit CPU core. My first proper tapeout.

Node: gf180mcuC
Tools used: Verilog, OpenLane, cocotb

Repo Bring-up Repo Post

TinyTapeout submissions

Many submissions to TinyTapeouts 2 and 3.5, most notably a custom 4-bit CPU and 8-bit MCU.

Node: sky130A
Tools used: Verilog, Logisim Evolution, OpenLane, GitHub Actions, cocotb

Repo & Docs Repo Repo Repo & Docs Repo Repo Repo Repo